An advanced CMOS EPROM technology for high speed/high density programmable logic devices and memory applications

Author

Hu, G.J. ; Madurawe, R.U. ; Cleeves, M. ; Dejenfelt, A. ; Pass, C. ; Carpenter, M. ; Zicolello, P. ; Malmfeldt, C. ; Norman, K.A.

Author_Institution

Cypress Semicond., San Jose, CA, USA

fYear

1994

fDate

1-4 May 1994

Firstpage

488

Lastpage

491

Abstract

A 0.65 μm double-level poly and metal UV EPROM CMOS technology has been developed for high speed complex Programmable Logic Device (PLD) and memory applications. Six types of transistors are used for the high performance designs. In addition to the design rule scaling, the new process includes poly buffer LOCOS (PBL) isolation, borderless contacts/vias. Half the die size and twice the speed on a high density MAX product has been demonstrated compared to a 0.8 μm technology

Keywords

CMOS memory circuits; EPROM; integrated circuit design; integrated circuit technology; isolation technology; memory architecture; programmable logic devices; 0.65 micron; CMOS EPROM technology; UV EPROM; borderless contacts/vias; design rule scaling; die size; double-level poly; high density programmable logic devices; memory applications; poly buffer LOCOS isolation; CMOS technology; EPROM; Etching; FETs; Isolation technology; Low voltage; Nonvolatile memory; Planarization; Programmable logic devices; Tungsten;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994

Conference_Location

San Diego, CA

Print_ISBN

0-7803-1886-2

Type

conf

DOI

10.1109/CICC.1994.379676

Filename

379676