DocumentCode
2489099
Title
Improved reliability of amorphous silicon anti-fuse used in high speed FPGA
Author
Nariani, Subhash R. ; Gabriel, Calvin T. ; Jain, Vivek
Author_Institution
VLSI Technol. Inc., San Jose, CA, USA
fYear
1994
fDate
1-4 May 1994
Firstpage
484
Lastpage
487
Abstract
A programmable anti-fuse, using amorphous silicon between levels of metal, is studied. The step coverage of the a-Si has the most significant impact on the anti-fuse characteristics. Other critical process parameters are also identified. The anti-fuse architecture is optimized to enhance its performance, yield and reliability with built-in process robustness
Keywords
amorphous semiconductors; circuit optimisation; field programmable gate arrays; integrated circuit reliability; integrated circuit yield; programmable logic arrays; silicon; Si; a-Si; amorphous silicon; built-in process robustness; critical process parameters; high speed FPGA; programmable anti-fuse; reliability; step coverage; yield; Amorphous silicon; Breakdown voltage; CMOS process; CMOS technology; Current measurement; Dielectrics; Electrical resistance measurement; Electrodes; Field programmable gate arrays; Robustness;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994
Conference_Location
San Diego, CA
Print_ISBN
0-7803-1886-2
Type
conf
DOI
10.1109/CICC.1994.379677
Filename
379677
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