Title :
Massively parallel neural signal processing: System-on-Chip design with FPGAs
Author :
Balasubramanian, Karthikeyan ; Obeid, Iyad
Author_Institution :
Neural Instrum. Lab., Temple Univ., Philadelphia, PA, USA
fDate :
Aug. 30 2011-Sept. 3 2011
Abstract :
This work discusses the architectural layout and performance results of a SoC design for parallel neural signal processing. Architectural framework for scalability and scalar reconfigurability are presented. Architectural requirements for massive parallelism in neural recordings are presented. Prototype architecture with dual processors and multi-level reconfigurable platform design is presented. Functional modules of the platform include real-time spike detector and sorter for several hundreds of neural channels. Performance of the platform for a 300 channel interface is also discussed.
Keywords :
field programmable gate arrays; medical signal detection; medical signal processing; neurophysiology; parallel architectures; reconfigurable architectures; system-on-chip; FPGA; SoC design; architectural framework; architectural layout; channel interface; dual processors; massively parallel neural signal processing; multilevel reconfigurable platform design; neural channels; neural recordings; prototype architecture; real-time spike detector; system-on-chip design; Field programmable gate arrays; Hardware; Parallel processing; Program processors; Real time systems; Signal processing; Signal processing algorithms; Action Potentials; Computers; Signal Processing, Computer-Assisted; Software;
Conference_Titel :
Engineering in Medicine and Biology Society, EMBC, 2011 Annual International Conference of the IEEE
Conference_Location :
Boston, MA
Print_ISBN :
978-1-4244-4121-1
Electronic_ISBN :
1557-170X
DOI :
10.1109/IEMBS.2011.6091141
