DocumentCode
2489334
Title
Slope considerations in probabilistic simulation
Author
Stamoulis, Georgios I. ; Hajj, Ibrahim N.
Author_Institution
Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
fYear
1994
fDate
1-4 May 1994
Firstpage
425
Lastpage
428
Abstract
Probabilistic simulation has been recently proposed for reliability analysis of CMOS circuits, such as electromigration, hot-carrier effects and average power. This paper presents an extension to the existing probabilistic simulation methods by incorporating the slope information into the analysis. This allows for an improved estimation of the average current and the delay
Keywords
CMOS logic circuits; circuit analysis computing; delays; electromigration; hot carriers; integrated circuit reliability; logic CAD; logic gates; CMOS circuits; average power; delay; electromigration; hot-carrier effects; probabilistic simulation; reliability analysis; slope information; Analytical models; Circuit simulation; Computational modeling; Delay effects; Delay estimation; Electromigration; Logic circuits; Probabilistic logic; Timing; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994
Conference_Location
San Diego, CA
Print_ISBN
0-7803-1886-2
Type
conf
DOI
10.1109/CICC.1994.379688
Filename
379688
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