Reference Clockless 3.2Gb/s Clock and Data Recovery Circuit for Data Interface Applications

In this paper, a 3.2Gb/s clock and data recovery (CDR) circuit for a high-speed serial link without the reference clock is described. It has a phase and frequency detector (PD and FD), which incorporates a half rate bang-bang type oversampling PD and a half- rate frequency detector that can achieve low-jitter operation and improve pull-in range. The PD of oversampling method finds a phase error by generating four phase up/down signals. The FD of quadri-correlator method finds a frequency error by generating frequency up/down signals. Therefore these six signals control three charge pump respectively. It also has a ring oscillator type voltage controlled oscillator (VCO) and three charge pumps (CP). The VCO consists of four fully differential delay cells with rail-to-rail current bias scheme that can increase the VCO tuning range and tuning linearity. The CDR circuit was designed using 0.18 um 1P6M CMOS process for implementation. The simulation results are shown that power consumption of the designed circuit was 160 m Wat 1.8 V supply voltage.