A fast single chip implementation of 8192 complex points FFT

Author

Bidet, E. ; Joanblanq, C. ; Senn, P.

Author_Institution

France Telecom, CNET, Grenoble, France

fYear

1994

fDate

1-4 May 1994

Firstpage

207

Lastpage

210

Abstract

This paper presents the first single chip dedicated to the computation of direct or inverse fast Fourier transforms of up to 8192 complex points. Due to its pipelined architecture, it can perform a 8 K FFT every 400 μs and a IK FFT every 50 μs. A new internal results scaling scheme has been introduced in order to optimize the SNR and to minimize the storage requirements. This component has been developed mainly for the validation of the Single Frequency Network concept in an COFDM digital terrestrial television system

Keywords

CMOS digital integrated circuits; application specific integrated circuits; digital signal processing chips; digital television; fast Fourier transforms; frequency division multiplexing; mathematics computing; pipeline arithmetic; telecommunication computing; 8192 complex points; COFDM digital terrestrial TV system; SNR optimisation; direct FFT; fast Fourier transforms; fast single chip implementation; internal results scaling scheme; inverse FFT; orthogonal FDM; pipelined architecture; single frequency network concept; storage requirements; triple-metal CMOS; Broadcasting; Computer architecture; Demodulation; Digital TV; Europe; Fast Fourier transforms; Frequency division multiplexing; OFDM modulation; Read-write memory; Telecommunication computing;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994

Conference_Location

San Diego, CA

Print_ISBN

0-7803-1886-2

Type

conf

DOI

10.1109/CICC.1994.379735

Filename

379735