High performance multi-channel data compression chip

This paper describes the architecture and implementation of the Data Compression Chip (DCC) for high-performance lossless data compression for multi-channel highspeed data networking applications. The DCC implements an improved adaptive string matching algorithm using a new parallel architecture-the Variable Length String Matcher (VLSM). The VLSM quickly performs an otherwise time-intensive string-matching procedure. Furthermore, by avoiding the typical data structures that require very large and fast memory to store a compression vocabulary, the DCC´s VLSM minimizes system costs. By maintaining separate vocabularies for multiple channels, the DCC eliminates the loss of compression efficiency otherwise experienced in typical frame-multiplexed or reset-at-frame applications. The DCC uses a high-performance algorithm with a custom parallel architecture to minimize vocabulary memory (VRAM) requirements and provide very high throughput and compression efficiency for multiple channels. The device has been realized in 0.8 micron CMOS technology with a die area of 9.27 mm×10.0 mm and power dissipation about 1 W at 20 MHz. It employs a 160 pin PQFP package