Improving cell libraries for synthesis

Author

Scott, Ken ; Keutzer, Kurt

Author_Institution

Synopsys Inc., Mountain View, CA, USA

fYear

1994

fDate

1-4 May 1994

Firstpage

128

Lastpage

131

Abstract

This paper examines the issues associated with building a cell library that will serve as the target for an automated synthesis tool and particularly focuses on cell library modifications that will improve the speed of a circuit. A number of library modifications are suggested here, and an experimental method for evaluating their effectiveness is described. This method is then used to quantify the importance of each modification as clearly as possible. The conclusion of this work is that relatively simple modifications in a cell library can lead to 20-30% improvements in final circuit speed, and that the principles motivating these modifications are not embodied in the cell sets of most commercial ASIC libraries

Keywords

application specific integrated circuits; integrated circuit design; logic CAD; logic arrays; logic design; logic gates; ASIC libraries; automated synthesis tool; cell libraries; cell sets; final circuit speed; library modifications; logic gates; logic synthesis; Application specific integrated circuits; Area measurement; Circuit synthesis; Costs; Force measurement; Libraries; Logic circuits; Power measurement; Solids; Velocity measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994

Conference_Location

San Diego, CA

Print_ISBN

0-7803-1886-2

Type

conf

DOI

10.1109/CICC.1994.379752

Filename

379752