Title :
Data flow processor for multi-standard video codec
Author :
Lee, Bang W. ; Kwon, Hyuk S. ; Kim, Bong N. ; Still, David ; Kopet, Tom ; Magar, Surendar
Author_Institution :
DSP Technol. Center, Samsung Electron. Co., KyungGi-Do, South Korea
Abstract :
In multimedia digital video applications, international standards such as JPEG, MPEG, and H.261 are widely adopted. Many DSP architectures have been proposed to meet requirements on the digital video. In this paper, a static data flow architecture containing nine parallel processors is described. Each processor made with a specialized hardware engine such as DCT and quantizer operates asynchronously and independently on its own data presence. This proposed DSP is fabricated in a 0.8 μm triple metal technology with 16×16 mm2 die area over 1.5 million transistors. The peak computing capability over 1 billion operations per second can provide full programmability for any DCT based digital video compression standards
Keywords :
data compression; digital signal processing chips; multimedia computing; multimedia systems; parallel processing; telecommunication standards; video codecs; 0.8 mum; 16 mm; DCT based digital video compression standards; DSP architectures; H.261; JPEG; MPEG; asynchronously; data flow processor; digital signal processing equipment; digital video; full programmability; independently; international standards; multi-standard video codec; multimedia digital video applications; parallel processors; peak computing capability; specialized hardware engine; static data flow architecture; transistors; triple metal technology; Computer architecture; Digital signal processing; Discrete cosine transforms; Image coding; Image quality; Transform coding; VLIW; Video codecs; Video compression; Videoconference;
Conference_Titel :
Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-1886-2
DOI :
10.1109/CICC.1994.379757
