Device-level analysis of a BiPMOS pull-down device structure for low-voltage dynamic BiCMOS VLSI

Author

Kuo, J.B. ; Su, K.W. ; Lou, J.H. ; Ma, S.Y. ; Chen, S.S. ; Chiang, C.S.

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

fYear

1994

fDate

1-4 May 1994

Firstpage

37

Lastpage

40

Abstract

This paper presents a device-level analysis of a BiPMOS pull-down structure for low-voltage dynamic BiCMOS logic gate circuit suitable for VLSI using sub-quarter-micron BiCMOS technology. Thanks to the BiPMOS pull-down structure, despite the slow turn-off of the bipolar device, the 1.5 V full-swing BiCMOS dynamic logic gate circuit shows a more than 1.8 times improvement in speed as compared to the CMOS static one

Keywords

BiCMOS digital integrated circuits; BiCMOS logic circuits; VLSI; combinational circuits; logic gates; transient analysis; 1.5 V; BiCMOS logic gate circuit; BiPMOS pull-down device structure; device-level analysis; full-swing BiCMOS dynamic logic gate; low-voltage dynamic VLSI; sub-quarter-micron BiCMOS technology; BiCMOS integrated circuits; CMOS logic circuits; CMOS technology; Logic circuits; Logic devices; Logic gates; Power supplies; Switches; Switching circuits; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994

Conference_Location

San Diego, CA

Print_ISBN

0-7803-1886-2

Type

conf

DOI

10.1109/CICC.1994.379771

Filename

379771