Title :
BEST2-a high performance super self-aligned 3 V/5 V BiCMOS technology with extremely low parasitics for low-power mixed-signal applications
Author :
Sung, J.M. ; Chui, T.Y. ; Lau, K. ; Lui, T.M. ; Archer, V.D. ; Razavi, B. ; Swartz, R.G. ; Erceg, F.M. ; Glick, J.T. ; Hower, G.R. ; Krafty, S.A. ; LaDuca, A.J. ; Ling, M.P. ; Moerschel, K.G. ; Possanza, W.A. ; Prozonic, M.A. ; Long, T.P.
Author_Institution :
AT&T Bell Labs., Holmdel, NJ, USA
Abstract :
We present AT&T BEST2 a high performance BiCMOS technology designed for supporting low-power multi-GHz mixed-signal applications. Processing modules reported include novel device structure fabrication, selective-epitaxy-capping of As buried layer, and deep fully-recessed LOCOS isolation. The developed process with relaxed design rules has achieved ft and fmax for npn bipolar (Ae=1×2 um2) or 23 GHz and 24 GHz at Vce=3 V, respectively. With BVceo⩾5.5 volts, and βVA product of 2400. Typical/minimum ECL gate delays are measured 48 ps/37 ps (Ae=1×2 um2: 500 mV swing) at 0.6 mA/2.1 mA stage current, and CMOS gate delay (gate oxide=125 A°, Leff=0.6 um; Vth,nch=0.45 V; V th,pch=-0.45 V) 70 ps/stage. BiCMOS phase-locked-loop (emitter width=1 um; gate Leff=0.7 um) has achieved a world record of 6 GHz operation at 2 V power supply with total power consumption of 60 mW
Keywords :
BiCMOS integrated circuits; integrated circuit measurement; integrated circuit technology; isolation technology; mixed analogue-digital integrated circuits; 0.6 mA; 2 V; 2.1 mA; 23 GHz; 24 GHz; 3 V; 37 ps; 48 ps; 6 GHz; 60 mW; AT&T; BEST2; CMOS gate delay; ECL gate delays; deep fully-recessed LOCOS isolation; device structure fabrication; low-power mixed-signal applications; parasitics; phase-locked-loop; selective-epitaxy-capping; super self-aligned BiCMOS technology; total power consumption; BiCMOS integrated circuits; Capacitance; Current measurement; Delay; Energy consumption; Fabrication; Isolation technology; Microelectronics; Power supplies; Process design;
Conference_Titel :
Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-1886-2
DOI :
10.1109/CICC.1994.379776
