Minimizing Peak Power Consumption during Scan Testing: Structural Technique for Don´t Care Bits Assignment

Scan architectures, though widely used in modern designs for testing purpose, are expensive in power consumption. In this paper, we first discuss the issues of excessive peak power consumption during scan testing. We next show that taking care of high current levels during the test cycle (i.e. between launch and capture) is highly relevant so as to avoid noise phenomena such as IR-drop or ground bounce. Then, we propose a solution based on power-aware assignment of don´t care bits in deterministic test patterns that considers structural information of the circuit under test. Experiments have been performed on ISCAS´89 and ITC´99 benchmark circuits. These results show that the proposed technique provides the best tradeoff between peak power reduction and increase of test sequence length