An Incremental Data Converter with an Oversampling Ratio of 3

Author

Caldwell, Trevor C. ; Johns, David A.

Author_Institution

Electr. & Comput. Eng., Toronto Univ., Ont.

fYear

0

fDate

0-0 0

Firstpage

125

Lastpage

128

Abstract

At low oversampling ratios, incremental ADCs are able to achieve a higher SNR than SigmaDelta modulators, allowing them to operate at oversampling ratios as low as 2-4 with high resolution. Furthermore, the removal of the input sample-and-hold significantly reduces the power consumption of incremental ADCs while slightly altering their signal transfer function. In this paper, the new application of incremental ADCs as high-speed data converters is demonstrated. A proposed 7th-order cascaded incremental ADC is analyzed and compared to a pipeline ADC, and it is shown that an incremental ADC can save half the analog power due to the removal of the input sample-and-hold and the reduced number of stages required for 12-bit operation

Keywords

analogue-digital conversion; sample and hold circuits; transfer functions; SigmaDelta modulators; analog power; analog-to-digital converter; high-speed data converters; incremental data converter; oversampling ratio; sample-and-hold; signal transfer function; Bandwidth; Clocks; Data conversion; Delta modulation; Energy consumption; Frequency; Pipelines; Sampling methods; Signal resolution; Transfer functions;

fLanguage

English

Publisher

ieee

Conference_Titel

Research in Microelectronics and Electronics 2006, Ph. D.

Conference_Location

Otranto

Print_ISBN

1-4244-0157-7

Type

conf

DOI

10.1109/RME.2006.1689912

Filename

1689912