• DocumentCode
    2491847
  • Title

    Low power storage cycle budget distribution tool support for hierarchical graphs

  • Author

    Brockmeyer, Erik ; Vandecappelle, Arnout ; Wuytack, Sven ; Catthoor, Francky

  • Author_Institution
    IMEC, Leuven, Belgium
  • fYear
    2000
  • fDate
    2000
  • Firstpage
    200
  • Lastpage
    206
  • Abstract
    In data-dominated applications, like multimedia and telecommunications applications, data storage and transfers are the most important factors in terms of energy consumption, area and system performance. Several steps which optimize these costs are present in our systematic “data transfer and storage exploration” methodology. In the important step discussed in this paper, the cycle budget available for background storage transfers is globally distributed over the application´s memory accesses that are typically grouped in the loop and function hierarchy. This is crucial for meeting the real-time constraints with a customized memory organisation without counteracting the memory size and energy budget optimizations achieved by earlier steps in our script. This paper proves the effectiveness of the prototype tool on driver applications of several application domains. It clearly shows the tradeoff between power, area and speed
  • Keywords
    graphs; memory architecture; optimisation; power consumption; real-time systems; storage management; background storage transfers; chip area; cost optimization; customized memory organisation; data storage; data transfer; data-dominated applications; driver applications; energy budget optimization; energy consumption; function hierarchy; globally distributed cycle budget; hierarchical graphs; loop hierarchy; low-power storage cycle budget distribution tool support; memory accesses; memory size optimization; multimedia applications; power/area/speed tradeoff; real-time constraints; storage exploration; system performance; telecommunications applications; Bandwidth; Constraint optimization; Cost function; Energy consumption; Memory architecture; Multimedia systems; Optimization methods; Prototypes; System performance; Telecommunications;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    System Synthesis, 2000. Proceedings. The 13th International Symposium on
  • Conference_Location
    Madrid
  • ISSN
    1080-1820
  • Print_ISBN
    0-7695-0765-4
  • Type

    conf

  • DOI
    10.1109/ISSS.2000.874050
  • Filename
    874050