Mapping array communication onto FIFO communication - towards an implementation

In high-throughput real-time media processing systems, the communication between processing units is typically specified as multi-dimensional arrays. However, the implementation of such applications is mostly FIFO (first-in, first-out) based. Mapping array communication onto a FIFO-based implementation requires complex address generators if the arrays have multiple dimensions. In this paper, we present a method for mapping array communication onto an efficient microcomputer architecture implementation based on FIFO communication via shared memory. A good hardware/software partitioning for the address generation is proposed. Furthermore, a complete design flow from specification to implementation is described. We illustrate this method with a design case: the communication of video frames between the front-end and the compressor in an MPEG encoder