A Novel Wide-Range Delay Cell for DLLs

Author

Ghaffari, Amir ; Abrishamifar, Adib

Author_Institution

Dept. of Electr. Eng., Iran Univ. of Sci. & Technol.

fYear

2006

fDate

19-21 Dec. 2006

Firstpage

497

Lastpage

500

Abstract

This paper describes a new architecture for delay cell that is used in the voltage-controlled delay line of analog delay locked loops. The proposed delay cell has differential configuration so it exhibits a good performance to supply and substrate noises. A wide operating range delay line is designed using this delay cell and in order to verify its operation, it is used in an analog DLL. The circuit design and ADS simulation are carried out by TSMC 0.18 mum CMOS process. Simulation results show that the frequency range of the delay line that use this delay cell is increased to 50% in comparison with previous architectures. Frequency range of the delay line is 120 to 420 MHz.

Keywords

CMOS integrated circuits; delay lock loops; integrated circuit design; 0.18 micron; 120 to 420 MHz; ADS simulation; CMOS process; TSMC; analog DLL; analog delay locked loops; circuit design; voltage controlled delay line; wide range delay cell; Circuit simulation; Clocks; Delay lines; Frequency; Inverters; Jitter; Phase detection; Phase noise; Signal to noise ratio; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical and Computer Engineering, 2006. ICECE '06. International Conference on

Conference_Location

Dhaka

Print_ISBN

98432-3814-1

Type

conf

DOI

10.1109/ICECE.2006.355677

Filename

4178513