Text-to-Braille Translator in a Chip

This paper describes the hardware implementation of a text to Braille translator using field-programmable gate arrays (FPGAs). Different from most commercial software-based translators, the circuit presented in this paper is able to carry out text-to-Braille translation in hardware. The translator is based on the translating algorithm, proposed by Paul Blenkhorn (1997). The very high speed hardware description language (VHDL) was used to describe the chip in a hierarchical way. The test results indicate that the hardware-based translator achieves the same results as software-based commercial translators, with superior throughput.