LAYGEN - Automatic Layout Generation of Analog ICs from Hierarchical Template Descriptions

Author

Lourengo, N. ; Vianello, M. ; Guilherme, Jose ; Horta, Nuno

Author_Institution

Inst. Superior Tecnico, Lisboa

fYear

0

fDate

0-0 0

Firstpage

213

Lastpage

216

Abstract

This paper describes an innovative analog IC layout generation tool based on evolutionary computation techniques. The proposed approach starts by a high level layout description (template), which is independent from technology, although including expert knowledge as placement and routing constrains. Then, based on the set of constrain rules provided by the designer through the template, the layout is automatically generated using an evolutionary kernel. Additionally, a module generated is also included in order to allow the automatic generation of different instances for each device in the layout template, therefore, automatically enlarging the solution search space. The LAYGEN tool is here presented and demonstrated for the layout generation of typical circuit structures

Keywords

analogue integrated circuits; evolutionary computation; high level synthesis; integrated circuit layout; LAYGEN tool; analog IC layout generation tool; analog integrated circuits; automatic layout generation; evolutionary computation; evolutionary kernel; hierarchical template descriptions; high level layout description; placement constrains; routing constrains; solution search space; Analog integrated circuits; Design automation; Electronic mail; Evolutionary computation; Guidelines; Integrated circuit layout; Kernel; Routing; Space technology; Telecommunications;

fLanguage

English

Publisher

ieee

Conference_Titel

Research in Microelectronics and Electronics 2006, Ph. D.

Conference_Location

Otranto

Print_ISBN

1-4244-0157-7

Type

conf

DOI

10.1109/RME.2006.1689934

Filename

1689934