A New Paradigm and Associated Tools for TLM/T Modeling of MPSoCs

Author

Viaud, Emmanuel ; Pêcheux, François

Author_Institution

Univ. Pierre & Marie Curie, Paris

fYear

0

fDate

0-0 0

Firstpage

217

Lastpage

220

Abstract

The paper presents a way to speed-up simulation of complex MPSoCs at the TLM/T (transaction level modeling with time) level and a way to switch from abstraction level "at run time". The hardware part of the platform is described in standard SystemC. Rather than using statistical models for adding timing, to obtain an accurate view of the platform dynamic contention is taken into account. This allows to reach a speed-up of up to 50 versus a corresponding BCA simulation with a low timing error. The state saving method gives the ability to save the state of a platform at the TLM/T level and move it to the same platform described at the BCA level. This allows fast and accurate debugging of the embedded software

Keywords

integrated circuit modelling; logic design; multiprocessing systems; system-on-chip; SystemC; TLM/T modeling; abstraction level; embedded software; multiprocessor system-on-chips; state saving method; statistical models; transaction level modeling; Abstracts; Access protocols; Computer architecture; Debugging; Embedded software; Hardware; Media Access Protocol; Space exploration; Switches; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Research in Microelectronics and Electronics 2006, Ph. D.

Conference_Location

Otranto

Print_ISBN

1-4244-0157-7

Type

conf

DOI

10.1109/RME.2006.1689935

Filename

1689935