A VHDL model and Implementation of a Coarse-Grain Reconfigurable Coprocessor for a RISC Core

This paper presents a coarse-grain reconfigurable machine used as a coprocessor to speed up the execution of computationally demanding tasks, which would be too heavy for a generic RISC core stand alone. A VHDL model of the proposed architecture has been created for simulation and implementation. Some common algorithms for signal processing and multimedia applications have been mapped over our design, to benchmark it and compare the results against another existing architecture. Synthesis results indicate that the area occupation and the operating frequency of our design are reasonable, guaranteeing the physical feasibility of our approach. The amount of clock cycles required to perform the considered algorithms on the proposed architecture is far smaller than the one needed by a RISC core alone running the same software, demonstrating the effectiveness of the proposed solution