HDL Library of Processing Units for an Automatic LDPC Decoder Design

Author

Falcão, Gabriel ; Gomes, Marco ; Gonçalves, João ; Faia, Pedro ; Silva, Vitor

Author_Institution

Inst. Telecom., Coimbra Univ.

fYear

0

fDate

0-0 0

Firstpage

349

Lastpage

352

Abstract

In this paper we propose an efficient and generic HDL library of processing units which are the key elements of a modular low-density parity check (LDPC) decoder design approach. General purpose, low complexity and high throughput bit node and check functional models are developed. Both full serial and parallel architectures are considered. Also, it is described an automatic HDL code generator for the proposed processing units using Matlab language and synthesis results for a Xilinx FPGA device are documented

Keywords

field programmable gate arrays; hardware description languages; microprocessor chips; parallel architectures; parity check codes; HDL library; LDPC decoder; Matlab language; Xilinx FPGA; automatic code generator; check functional models; full serial architecture; low-density parity check decoder; parallel architecture; Block codes; Computer languages; Field programmable gate arrays; Hardware design languages; Iterative algorithms; Iterative decoding; Libraries; Mathematical model; Parity check codes; Telecommunications;

fLanguage

English

Publisher

ieee

Conference_Titel

Research in Microelectronics and Electronics 2006, Ph. D.

Conference_Location

Otranto

Print_ISBN

1-4244-0157-7

Type

conf

DOI

10.1109/RME.2006.1689967

Filename

1689967