Improved parameterized efficient FPGA implementations of parallel 1-D filtering algorithms using Xilinx System Generator

Two hardware architectures are developed via an improved parameterized efficient FPGA implementation method for parallel 1-D real-time signal filtering algorithms to provide higher performance per Watt and minimum logic area at maximum frequency. This improvement is evidently manifested rapid system-level abstraction FPGA prototyping and optimized speed, area and power, targeting Virtex-6xc6vlX130Tl-1lff1156 FPGA board to achieve lower power consumption of (820 mW) and a (27%-44%) less device utilization at a maximum frequency of up to (231 MHz) using Xilinx System Generator. The improved parameterized FPGA implementation is a system-level abstraction of hardware-oriented parallel programming, as an alternative to gate-level Hardware Descriptive Language (HDL), to satisfy the high performance computation of parallel multidimensional filtering algorithms at a minimal development-to-market time.