Using MOEA to evolve a combinational circuit on a FPGA chip

A combinational circuit design method that can be completely implemented on a FPGA is presented. For carrying out faster evolution in evolutionary circuit design, a sub population based MOEA (multiobjective evolutionary algorithm) is employed in which the reconfigurable circuit (RC) architecture is encoded by Cartesian Genetic Programming (CGP). For hardware implementation, the Celoxica RC1000 PCI is employed which includes Xilinx Virtex xcv 2000E FPGA chip. This PCI card is communicating with host PC and acting as an evolvable platform. MOEA adopted modules are designed into a FPGA chip for discussing the rationality of circuit design method. Results of direct evolution and results of incremental evolution is compared, it shows MOEA is most efficient in the aspect of speeding up the convergence of evolution.