Deep Sub-100 nm Design Challenges

Author

Furuyama, Tohru

Author_Institution

Center for Semicond. Res. & Dev., Toshiba Corp.

fYear

0

fDate

0-0 0

Firstpage

9

Lastpage

16

Abstract

This paper will describe the problems in the design and development of deep sub-100 nm system LSI´s and/or SoC´s from different aspects. One of the most difficult problems is the large power consumption, in both active and stand-by modes. Another problem is how to improve the efficiency in the development of large scale chips and related softwares. Lithography, that has been getting harder and harder, is also an issue. It directly impacts the chip fabrication yield. Several approaches to counteract these problems mentioned above will be discussed; various low power technologies from device, circuit to architecture view points, high-level language based design flow and platform based IP reuse, and DFM (design for manufacturing) related technologies

Keywords

design for manufacture; hardware-software codesign; integrated circuit design; large scale integration; low-power electronics; nanolithography; system-on-chip; chip fabrication; deep sub-100 nm system LSI design; deep sub-100 nm system SoC design; design for manufacturing; high-level language based design flow; large scale chip development; lithography; low power technology; platform based IP reuse; power consumption; software development; Atomic layer deposition; Dielectrics and electrical insulation; Energy consumption; Large scale integration; Leakage current; MOSFET circuits; Production; Research and development; Silicon; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Digital System Design: Architectures, Methods and Tools, 2006. DSD 2006. 9th EUROMICRO Conference on

Conference_Location

Dubrovnik

Print_ISBN

0-7695-2609-8

Type

conf

DOI

10.1109/DSD.2006.37

Filename

1690015