Title :
Evaluating Dataflow and Pipelined Vector Processing Architectures for FPGA Co-processors
Author :
Freeman, Michael
Author_Institution :
Dept. of Comput. Sci., York Univ.
Abstract :
This paper describes the development of FPGA based co-processor architecture for accelerating vector comparisons e.g. Euclidean distance. In this paper we compare traditional pipelined and data/low implementations, in terms of processing speed and area requirements. Processing performance is compared against a software implementation to evaluate possible speedup
Keywords :
coprocessors; data flow computing; field programmable gate arrays; pipeline processing; vector processor systems; Euclidean distance; FPGA co-processor architecture; dataflow evaluation; pipelined vector processing architecture; Centralized control; Clocks; Computer architecture; Coprocessors; Euclidean distance; Field programmable gate arrays; Hardware; Parallel processing; Software performance; Spatial databases;
Conference_Titel :
Digital System Design: Architectures, Methods and Tools, 2006. DSD 2006. 9th EUROMICRO Conference on
Conference_Location :
Dubrovnik
Print_ISBN :
0-7695-2609-8
DOI :
10.1109/DSD.2006.51
