• DocumentCode
    2494219
  • Title

    Novel Modulo 2^n + 1 Multipliers

  • Author

    Vergos, H.T. ; Efstathiou, C.

  • Author_Institution
    Dept. of Comput. Eng. & Inf., Patras Univ., Patras, Greece
  • fYear
    0
  • fDate
    0-0 0
  • Firstpage
    168
  • Lastpage
    175
  • Abstract
    A new modulo 2n+1 multiplier architecture is proposed for operands in the normal representation. The novel architecture is derived by showing that all required correction factors can be merged into a single constant one and by treating this, partly as a partial product and partly by the final parallel adder. The proposed architecture utilizes a total of (n+1) partial products, each n bits wide and is built using an inverted end-around-carry, carry-save adder tree and a final parallel adder.
  • Keywords
    adders; carry logic; logic design; multiplying circuits; trees (mathematics); carry-save adder tree; correction factors; final parallel adder; inverted end-around-carry; modulo 2n+1 multiplier architecture; partial product; Adders; Circuits; Computer architecture; Convolution; Cryptography; Digital arithmetic; Digital systems; Fault tolerant systems; Informatics; Signal processing algorithms;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Digital System Design: Architectures, Methods and Tools, 2006. DSD 2006. 9th EUROMICRO Conference on
  • Conference_Location
    Dubrovnik
  • Print_ISBN
    0-7695-2609-8
  • Type

    conf

  • DOI
    10.1109/DSD.2006.71
  • Filename
    1690036
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2494219