Title :
An Asynchronous PLA with Improved Security Characteristics
Author :
Oikonomakos, Petros ; Moore, Simon
Author_Institution :
Comput. Lab., Cambridge Univ.
Abstract :
Programmable logic arrays (PLAs) present an alternative to logic-gate based design. We propose the transistor level structure of a PLA for single-rail asynchronous applications. The geometrically regular layout together with the deployment of dynamic logic help us fine-tune the PLA to enhance its resistance to side-channel attacks, while parity prediction and checking is employed to protect against malicious fault injection. Finally, we demonstrate how our PLAs can be used as building blocks of large-scale systems with good security characteristics, when combined with special return-to-zero asynchronous latches
Keywords :
fault diagnosis; logic design; logic gates; logic testing; programmable logic arrays; asynchronous PLA; logic-gate based design; malicious fault injection; parity prediction; programmable logic arrays; security characteristics; transistor level structure; Clocks; Energy consumption; Equations; Laboratories; Large-scale systems; Logic devices; Power system security; Programmable logic arrays; Protection; Timing;
Conference_Titel :
Digital System Design: Architectures, Methods and Tools, 2006. DSD 2006. 9th EUROMICRO Conference on
Conference_Location :
Dubrovnik
Print_ISBN :
0-7695-2609-8
DOI :
10.1109/DSD.2006.22
