A Mixed Language Fault Simulation of VHDL and SystemC

Fault simulation technology is essential key not only to the validation of test patterns for ICs and SoCs, but also to the analysis of system behavior under fault transient and intermittent faults. For this purpose, we developed a hierarchical fault simulation environment that uses structural VHDL models at the gate level, but is able to model embedded blocks in C++. With SystemC becoming a de-facto standard in high-level modeling, a simulation approach had to be developed which makes effective use of SystemC technology by encapsulating such "threads" into the fault simulation environment. Furthermore, it can be shown that SystemC allows the modeling of complex transistor-level structures, for which equivalent gate-level representations are not adequate