Abstract Application Modeling for System Design Space Exploration

The increasing complexity of system-on-chip (SoC) requires a complete reexamination of design and validation methods prior to final implementation whereas faster system design space exploration is today´s requirement to speed up the design process in order to cope with ´time-to-market´ constraint. We have introduced SoC modeling approach which mixes simulation and formal modeling and verification methods for efficient design space exploration phase of SoC design cycle. The applications are described as a network of communicating tasks whose behaviors are abstracted. Because applications are abstract, it is possible to significantly increase the speed of simulation, to perform a quick performance analysis and apply static formal analysis techniques at higher level of abstraction. The proposed methodology has been employed in the design of a telecommunication system. A part of the application is modeled as a set of tasks in a modeling language and their behavior is monitored as a waveform of events in a simulation environment