Title :
Cascade Scheme for Concurrent Errors Detection
Author :
Levin, Ilya ; Ostrovsky, Vladimir ; Keren, Osnat ; Sinelnikov, Vladimir
Author_Institution :
Tel Aviv Univ.
Abstract :
The paper deals with synthesis technique for designing circuits with cascade errors detection. The proposed technique is based on partitioning a scheme into a number of cascades followed by parity checking their output logic. The algorithm for partitioning the scheme into cascades is provided. An universal scheme of finite state machine (FSM) with the cascade errors detection is presented and investigated. The scheme does not require any redundant coding variables. Benchmark results are presented and show significantly low overhead requirement
Keywords :
error detection codes; finite state machines; high level synthesis; logic partitioning; logic testing; parity check codes; FSM; circuit design synthesis technique; concurrent cascade error detection; finite state machine; output logic parity checking; Automata; Circuit faults; Circuit synthesis; Fault detection; Gallium nitride; Instruments; Inverters; Logic; Partitioning algorithms; Pins;
Conference_Titel :
Digital System Design: Architectures, Methods and Tools, 2006. DSD 2006. 9th EUROMICRO Conference on
Conference_Location :
Dubrovnik
Print_ISBN :
0-7695-2609-8
DOI :
10.1109/DSD.2006.31
