A Low-Offset and Low-Power CMOS Front-End Circuit for Physiological Signal Acquisition

There is a growing demand of high-precision and low-power ICs for physiological signal acquisitions. One of the crucial functional blocks for such ICs is the analogue front-end circuit. In this paper we presented a compact analogue front-end circuit with adjustable gains that is elaborated for various physiological signal acquisitions. The circuit we have developed consists of a gain programmable instrumentation amplifier (GPIA), a current-to-voltage converter (I-V converter) and a high-precision reference. The circuit was designed using the SMIC 0.18 mum mixed-signal CMOS 1P6M process technology, with a silicon area of 356 mum times 105 mum. Back-end simulation results suggested that the circuit achieved a common-mode-rejection-ration (CMRR) of 142 dB, the adjustable gain from 31.6 dB to 76.5 dB, and the offset voltage less than 80 muV. The power consumption of the GPIA was approximately 113.4 muW under a 1.8 V power supply.