Design and Implementation of Low-Area and Low-Power AES Encryption Hardware Core

Author

Hämäläinen, Panu ; Alho, Timo ; Hännikäinen, Marko ; Hämäläinen, Timo D.

Author_Institution

Inst. of Digital & Comput. Syst., Tampere Univ. of Technol.

fYear

0

fDate

0-0 0

Firstpage

577

Lastpage

583

Abstract

The Advanced Encryption Standard (AES) algorithm has become the default choice for various security services in numerous applications. In this paper we present an AES encryption hardware core suited for devices in which low cost and low power consumption are desired. The core constitutes of a novel 8-bit architecture and supports encryption with 128-bit keys. In a 0.13 mum CMOS technology our area optimized implementation consumes 3.1 kgates. The throughput at the maximum clock frequency of 153 MHz is 121 Mbps, also in feedback encryption modes. Compared to previous 8-bit implementations, we achieve significantly higher throughput with corresponding area. The energy consumption per processed block is also lower

Keywords

CMOS integrated circuits; application specific integrated circuits; cryptography; low-power electronics; 8-bit architecture; ASIC; Advanced Encryption Standard algorithm; CMOS technology; application specific integrated circuit; clock frequency; energy consumption; feedback encryption modes; low power consumption; low-area AES encryption hardware; low-power AES encryption hardware core; security services; CMOS technology; Clocks; Costs; Cryptography; Energy consumption; Feedback; Frequency; Hardware; Security; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Digital System Design: Architectures, Methods and Tools, 2006. DSD 2006. 9th EUROMICRO Conference on

Conference_Location

Dubrovnik

Print_ISBN

0-7695-2609-8

Type

conf

DOI

10.1109/DSD.2006.40

Filename

1690090