Analysis of gate misalignment effect on the threshold voltage of double-gate (DG) ultrathin fully-depleted (FD) silicon-on-insulator (SOI) NMOS devices using a compact model considering fringing electric field effect

Author

Kuo, J.B. ; Sun, E.C. ; Lin, M.T.

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

fYear

2003

fDate

17-18 Nov. 2003

Firstpage

83

Lastpage

86

Abstract

This paper reports an analysis of gate misalignment effect on the threshold voltage of double-gate ultrathin fully depleted (FD) silicon on insulator (SOI) NMOS devices using a compact model considering fringing electric field effect. Using the conformal mapping transformation approach, a closed-form compact model considering the fringing electric filed effect above the non-gate overlap region has been derived to provide an accurate prediction of the threshold voltage behavior as verified by the 2D simulation results.

Keywords

MOS integrated circuits; conformal mapping; electric field effects; semiconductor device models; silicon-on-insulator; simulation; 2D simulation; NMOS devices; circuit simulation; conformal mapping transformation; double-gate ultrathin fully-depleted silicon-on-insulator; fringing electric field effect; gate misalignment effect; non-gate overlap region; threshold voltage; Analytical models; Equations; MOS devices; Silicon on insulator technology; Threshold voltage; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices for Microwave and Optoelectronic Applications, 2003. EDMO 2003. The 11th IEEE International Symposium on

Print_ISBN

0-7803-7904-7

Type

conf

DOI

10.1109/EDMO.2003.1259988

Filename

1259988