Title :
FPGA implementation of LDPC encoder with approximate lower triangular matrix
Author :
Chen, Hua ; Hsiao, Jue Hsuan ; He, Jheng Shyuan
Author_Institution :
Oriental Inst. of Technol., Inst. of Inf. & Commun. Eng., Taipei, Taiwan
Abstract :
This study used the weight (3, 6) approximate lower triangular regular parity check matrix to implement the LDPC encoding on the 5641R FPGA of the Software Define Radio system developed by National Instruments (NI) [1]. This study provided a detailed introduction to the encoding mechanism of the approximate lower triangular LDPC, and completed the implementation and verification of FPGA hardware.
Keywords :
approximation theory; field programmable gate arrays; parity check codes; software radio; FPGA implementation; LDPC encoder; NI; National Instruments; software define radio system; weight approximate lower triangular regular parity check matrix; Channel coding; Field programmable gate arrays; Matrix converters; Parity check codes; Sparse matrices; Vectors; Approximate Lower Triangular; LDPC; SDR;
Conference_Titel :
Consumer Electronics (GCCE), 2012 IEEE 1st Global Conference on
Conference_Location :
Tokyo
Print_ISBN :
978-1-4673-1500-5
DOI :
10.1109/GCCE.2012.6379546
