DocumentCode :
2495617
Title :
FPGA implementation of a support vector machine for classification and regression
Author :
Ruiz-Llata, Marta ; Guarnizo, Guillermo ; Yébenes-Calvino, Mar
Author_Institution :
Dept. of Electron. Technol., Univ. Carlos III de Madrid, Leganés, Spain
fYear :
2010
fDate :
18-23 July 2010
Firstpage :
1
Lastpage :
5
Abstract :
We present a successful design for a high-performance, low-resource-consuming hardware for Support Vector Classification and Support Vector Regression. The system has been implemented on a low cost FPGA device and exploits the advantages of parallel processing to compute the feed forward phase in support vector machines. In this paper we show that the same hardware can be used for classification problems and regression problems, and we show satisfactory results on an image recognition problem by SV multiclass classification and on a function estimation problem by SV regression.
Keywords :
field programmable gate arrays; image classification; regression analysis; support vector machines; SV multiclass classification; SV regression; feedforward phase; function estimation problem; image recognition problem; low cost FPGA device; parallel processing; support vector classification; support vector machine; support vector regression; Clocks; Field programmable gate arrays; Hardware; Kernel; Support vector machine classification; Training;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Neural Networks (IJCNN), The 2010 International Joint Conference on
Conference_Location :
Barcelona
ISSN :
1098-7576
Print_ISBN :
978-1-4244-6916-1
Type :
conf
DOI :
10.1109/IJCNN.2010.5596820
Filename :
5596820
Link To Document :
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