DocumentCode :
2495756
Title :
Microfilled via: an enabling technology for high density high performance high volume BGA substrates
Author :
Chiang, Steve ; Lan, James ; Shepherd, Bill ; Wu, Paul Y F
Author_Institution :
ProLinx Labs Corp., San Jose, CA, USA
fYear :
1996
fDate :
14-16 Oct 1996
Firstpage :
66
Lastpage :
69
Abstract :
Microfilled Via (MfVia) is an enabling technology on which a superior and economical BGA substrate manufacturing is based. The main technology feature is a new method of creating a micro via by substituting the traditional costly drilling and plating process with a mass photoimageable via hole creation and stencil hole filling process. Via holes are later covered by copper through a foil lamination process to create a flat surface. Besides a dramatic reduction in the manufacturing cost, the new process also provides the following advantages: (1) True pad on via, (2) Superior Cu to photoimageable dielectric adhesion due to the lamination process, (3) High density outer layer process as the extra Cu plating on the outer layer is eliminated, (4) Low cost blind and buried via due to the sequential layer buildup and photo imaged vias. This high density via technology allows easy implementation of high pin-count substrates, even with the current generation line and spacing rule, such as 0.004"/0.004". This paper discusses the manufacturing, characterization and reliability of a BGA package manufactured using the microfilled via technology
Keywords :
integrated circuit manufacture; integrated circuit packaging; integrated circuit reliability; laminates; microassembling; thermal analysis; 0.004 in; BGA package; BGA substrate manufacturing; Cu; ball grid array; foil lamination process; high density BGA substrates; high density via technology; high pin-count substrates; high volume BGA substrates; mass photoimageable via hole creation; microfilled via technology; photoimageable dielectric adhesion; reliability; stencil hole filling process; Adhesives; Copper; Costs; Dielectrics; Drilling; Filling; Lamination; Manufacturing processes; Packaging; Pulp manufacturing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics Manufacturing Technology Symposium, 1996., Nineteenth IEEE/CPMT
Conference_Location :
Austin, TX
ISSN :
1089-8190
Print_ISBN :
0-7803-3642-9
Type :
conf
DOI :
10.1109/IEMT.1996.559683
Filename :
559683
Link To Document :
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