A methodology for minimum area cellular automata generation

Author

Cardoso, Paulo Sergio ; Strum, Marius ; de A.Amazonas, J.R. ; Chau, Wang Jiang

Author_Institution

Dept. de Engenharia Electron., Sao Paulo Univ., Brazil

fYear

1998

fDate

2-4 Dec 1998

Firstpage

33

Lastpage

37

Abstract

Cellular automata (CAs) have been adopted in several VLSI applications to generate pseudo-random sequences. CAs should be able to generate maximum cycle length pseudo-random sequences. As they are built into high performance VLSI chips they should also present minimum area. Previous works on CAs generation have failed, up to now, to solve the problem. In this paper we present a “guided search” methodology to generate such minimum area CAs. Results are compared to the ones obtained in previous works and the area gain reported

Keywords

VLSI; automatic test pattern generation; binary sequences; built-in self test; cellular automata; integrated circuit testing; ATPG; BIST; VLSI applications; area gain; cellular automata generation; guided search; maximum cycle length; minimum area cellular automata; pseudo-random sequences; Automata; Automatic test pattern generation; Automatic testing; Built-in self-test; Circuit testing; Content addressable storage; Equations; Linear feedback shift registers; Polynomials; Spread spectrum communication; Test pattern generators; Yttrium;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 1998. ATS '98. Proceedings. Seventh Asian

ISSN

1081-7735

Print_ISBN

0-8186-8277-9

Type

conf

DOI

10.1109/ATS.1998.741577

Filename

741577