A multi-cache coherence scheme for shuffle-exchange network based multiprocessors

As VLSI technology continues to increase the speed of microprocessors, their effective use in a shared memory multiprocessor model has become a primary challenge. This has placed greater burden on the interconnection network which must efficiently satisfy the bandwidth requirements of these powerful processors at an effective cost. In this paper, we evaluate the performance of a memory-coherent single-stage shuffle-exchange network based multiprocessor. Each network node contains a small global cache memory and a routing directory. The routing directory is used to implement an adaptive single copy coherence scheme which regulates the dynamic movement of the shared data blocks according to the access patterns exhibited in memory reference streams. We use simulation to measure the performance of the protocol and compare it against multiple copy schemes designed for systems employing multistage interconnection networks