FPGA implementation of low-profile wake-up radio receiver for Wireless Sensor Networks

Achieving low power consumption, size reduction, increased efficiency, and space optimization are all challenges in Wireless Sensor Networks (WSNs). WSNs use duty cycle to improve its power efficiency, and wake-up radio (WUR) is used as a control channel to wake up WSN nodes. With its highly flexible features, a field-programmable gate array (FPGA) is one of the attractive candidates for implementing part of WSN devices, and previous works have demonstrated its suitability. In this work, we propose a low-profile WUR scheme and implemented its receiver components using FPGA. The low-profile WUR wakes up the rest of the WUR module of the recipient node only and eliminate unnecessary WUR-module activation of non-recipient nodes. Experimental results of implementing module show that the proposed solution can significantly eliminate unnecessary power consumption.