DocumentCode
2496342
Title
Switches and switch interconnects
Author
Ni, Lionel M. ; Qiao, Wenjian ; Yang, Mingyao
Author_Institution
Dept. of Comput. Sci., Michigan State Univ., East Lansing, MI, USA
fYear
1997
fDate
22-24 June 1997
Firstpage
122
Lastpage
129
Abstract
Switched networks are receiving much attention and supplying a major class of interconnect networks. This paper discusses major issues in switch design and switch interconnects. Due to the importance of high-speed switches in building switched LANs, major design issues are studied and several commercial switches are reviewed. Among different techniques used in switch design, cut-through switching promises short latency delivery and thus is well suited to distributed/parallel applications. The back pressure flow control of cut-through switching also prevents packet loss due to buffer overflow. For economical and practical reasons, switch interconnects should support irregular topologies, which makes deadlock-free routing more difficult. To provide good network performance, a key point is to develop a traffic-balanced network with minimum diameter and average path length. It is important to understand the issues and solutions in these areas in order to meet the increasing performance demand.
Keywords
LAN interconnection; concurrency control; performance evaluation; switched networks; average path length; buffer overflow; cut-through switching; deadlock-free routing; irregular topologies; network performance; performance demand; short latency delivery; switch design; switch interconnects; switched LANs; switched networks; traffic-balanced network; Buffer overflow; Buildings; Delay; LAN interconnection; Network topology; Packet switching; Pressure control; Routing; Switches; System recovery;
fLanguage
English
Publisher
ieee
Conference_Titel
Massively Parallel Processing Using Optical Interconnections, 1997., Proceedings of the Fourth International Conference on
Print_ISBN
0-8186-7975-1
Type
conf
DOI
10.1109/MPPOI.1997.609151
Filename
609151
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