Title :
On a logical fault model H1SGLF for enhancing defect coverage
Author :
Sang, Junzhi ; Shinogi, Tsuyoshi ; Takase, Hamhiko ; Hayashi, Temmine
Author_Institution :
Fac. of Eng., Mie Univ., Tsu, Japan
Abstract :
This paper presents a logical fault model, the single gate logical fault with Hamming distance 1 (HISGLF) model, designed to enhance the defect coverage of test sets. Although some characteristics of the HISGLF model are similar to those of the single stuck-at fault (SSAF) model, a test set derived from the HISGLF model is capable of covering more defects than one derived from the SSAF model. Most of the existing ATPGs for the SSAF model can be easily modified for the H1SGLF model. Experimental results show the effectiveness of the fault model
Keywords :
automatic test pattern generation; fault simulation; logic testing; ATPG; H1SGLF model; Hamming distance; defect coverage enhancement; logical fault model; single gate logical fault; test sets; Circuit faults; Circuit testing; Design engineering; Electrical capacitance tomography; Electrical fault detection; Fault detection; Hamming distance; Integrated circuit testing; Logic testing; Read only memory; System testing; Test pattern generators;
Conference_Titel :
Test Symposium, 1998. ATS '98. Proceedings. Seventh Asian
Print_ISBN :
0-8186-8277-9
DOI :
10.1109/ATS.1998.741598
