Title :
PowerRanger: Assessing circuit vulnerability to power attacks using SAT-based static analysis
Author :
Hao, Jeff ; Bertacco, Valeria
Author_Institution :
Dept. of Comput. Sci. & Eng., Univ. of Michigan, Ann Arbor, MI, USA
Abstract :
Cryptographic cores, though algorithmically secure, can leak information about their operation during execution. By monitoring the power dissipation of a core, an attacker can extract secret keys used for encryption. To guard against this, designers must minimize the variation of power dissipation of their circuits over time. Unfortunately, power dissipation is a complex function of several different factors, and an exhaustive search for its maximum range is computationally infeasible. In this paper, we propose PowerRanger, a technique based on Boolean satisfiability to produce tight upper and lower bounds on both maximum and minimum power dissipation. In addition, we incorporate min-cut partitioning in our solution to improve its scalability for large designs. We evaluated the quality and performance of PowerRanger on a number of ISCAS benchmarks, as well as two cryptographic cores, showing that our technique significantly outperforms previously known solutions.
Keywords :
Boolean algebra; computability; cryptography; microprocessor chips; Boolean satisfiability; ISCAS benchmarks; PowerRanger; SAT-based static analysis; circuit vulnerability assessment; cryptographic cores; min-cut partitioning; power attack; power dissipation; Algorithm design and analysis; Cryptography; Delay estimation; Digital circuits; Energy consumption; Frequency estimation; Information analysis; Partitioning algorithms; Power dissipation; Scalability; Boolean Satisfiability; Partitioning; Power Analysis; Power Estimation; Security;
Conference_Titel :
High Level Design Validation and Test Workshop, 2009. HLDVT 2009. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-4823-4
Electronic_ISBN :
1552-6674
DOI :
10.1109/HLDVT.2009.5340174