• DocumentCode
    2496588
  • Title

    Analysis of high performance RF integrated passive circuits using the glass substrate

  • Author

    Wang, Chen-Chao ; Yang, Hsueh-An ; Shyu, Ying-Chieh ; Li, Meng-Hsun ; Chiu, Chi-Tsung ; Wu, Sung-Mao ; Kuo, Chih-Wen ; Hung, Chih-Pin

  • Author_Institution
    Corp. R&D, Adv. Semiconductor Eng. Inc., Kaohsiung
  • fYear
    2008
  • fDate
    1-2 Dec. 2008
  • Firstpage
    135
  • Lastpage
    138
  • Abstract
    This paper describes the design, modeling, simulation, and fabrication of wafer level integrated passive devices (IPDs). These IPDs, comprising of a resistor, capacitor, and inductor, have been developed in the thin-film and thick metallization processing technology on silicon or high-resisitivity substrate. The electrical equivalent model of the single component structures is presented for design and scalable modeling, and the accurance is demonstrated by measurement. The fabrication method, new circuit design and materials of these devices or substrate lead to improve characteristics suitable for application in high-frequency RF module or system. The fabricated balanced-BPF have insertion loss less than 2.0 dB with die size of 2.1 mm by 1.4 mm for band range (2300 MHz-2700 MHz).
  • Keywords
    UHF integrated circuits; equivalent circuits; integrated circuit design; integrated circuit metallisation; integrated circuit modelling; passive networks; thick film circuits; thin film circuits; wafer level packaging; electrical equivalent model; electronic packaging; frequency 2300 MHz to 2700 MHz; glass substrate; high performance RF integrated passive circuits; high-frequency RF module; scalable modeling; single component structures; size 1.4 mm; size 2.1 mm; thick metallisation processing technology; thin film metallization; wafer level integrated passive devices; Circuit simulation; Fabrication; Glass; Passive circuits; Performance analysis; Radio frequency; Resistors; Semiconductor device modeling; Substrates; Thin film inductors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Packaging Workshop of Japan, 2008. VPWJ 2008. IEEE 9th
  • Conference_Location
    Kyoto
  • Print_ISBN
    978-1-4244-3498-5
  • Type

    conf

  • DOI
    10.1109/VPWJ.2008.4762233
  • Filename
    4762233