DocumentCode :
2496613
Title :
Learning from constraints for formal property checking
Author :
Moon, In-Ho ; Harer, Kevin
fYear :
2009
fDate :
4-6 Nov. 2009
Firstpage :
38
Lastpage :
45
Abstract :
Constraints are commonly used in both simulation and formal verification in order to specify expected input conditions and state transitions. Constraint solving is a process to determine input vectors which satisfy the set of constraints during constrained random simulation. Even though constraints are used in formal property checking to restrict the search space, constraint solving has never had direct application to formal property checking. There are often many simple, yet powerful, invariants that can be learned from constraint solving during constrained random simulation. These invariants are shown in this paper to significantly simplify the formal verification problem. We use approximate constraint solving to compute an approximate set of valid input vectors. The approximate set of valid input vectors are a strict superset of the set of all legal input vectors. We use BDD techniques to compute these input vectors during constrained random simulation, then process the resulting BDDs for learning invariants which can be used during formal property checking. This paper presents efficient BDD algorithms to learn invariants from the BDDs generated from approximate constraint solving. We also present how these learned invariants can be applied to the formal property checking. Experimental results show that invariants learned during constraint solving can significantly improve the performance of formal property checking with many industrial designs.
Keywords :
binary decision diagrams; constraint handling; formal verification; approximate constraint solving; constrained random simulation; constraint solving; formal property checking; formal verification; Binary decision diagrams; Boolean functions; Computational modeling; Cost accounting; Data structures; Formal verification; Law; Legal factors; Logic design; Moon;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
High Level Design Validation and Test Workshop, 2009. HLDVT 2009. IEEE International
Conference_Location :
San Francisco, CA
ISSN :
1552-6674
Print_ISBN :
978-1-4244-4823-4
Electronic_ISBN :
1552-6674
Type :
conf
DOI :
10.1109/HLDVT.2009.5340176
Filename :
5340176
Link To Document :
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