Static test compaction for scan-based designs to reduce test application time

We propose a static compaction procedure to reduce the test application time for full and partial scan synchronous sequential circuits. The procedure accepts as input a set of test subsequences. For every subsequence, it also accepts the vector to be scanned-in before the subsequence is applied. The procedure uses two operations to reduce the test application time. The first operation combines test subsequences. The second operation reduces the lengths of the combined subsequences. The reductions in test application time of the proposed procedure are demonstrated through experimental results