A CMOS power amplifier for 5.8GHz DSRC application

Author

Feiyan, Xing ; Ling, Sun ; Yanjun, Peng

Author_Institution

Jiangsu Key Lab. of ASIC Design, Nantong Univ., Nantong, China

Volume

5

fYear

2012

fDate

5-8 May 2012

Firstpage

1

Lastpage

4

Abstract

Based on TSMC 0.18-μm CMOS process, a 5.8-GHz CMOS power amplifier for DSRC application is investigated in this paper. The proposed power amplifier is consisted of two stages which are followed by input, output and inter-stage matching networks. Capacitance compensation technique is employed to improve the linearity of the output stage power amplifier. Simulation results show that the designed power amplifier with low voltage operation of 1.8 V can achieve linear power gain of 16.9 dB, 1 dB compression power output of 17.6 dBm, third order inter-modulation distortion (IMD3) of -43 dBc at the output power of 10 dBm, which has about 8 dB improvement compared with the structure without the capacitance compensation technique.

Keywords

CMOS analogue integrated circuits; MMIC amplifiers; compensation; field effect MMIC; intermodulation distortion; CMOS power amplifier; DSRC; IMD3; TSMC CMOS process; capacitance compensation technique; dedicated short range communication system; frequency 5.8 GHz; gain 16.9 dB; interstage matching networks; linear power gain; output stage power amplifier; size 0.18 mum; third order intermodulation distortion; voltage 1.8 V; CMOS integrated circuits; CMOS technology; Capacitance; Impedance matching; Linearity; Logic gates; Power amplifiers;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave and Millimeter Wave Technology (ICMMT), 2012 International Conference on

Conference_Location

Shenzhen

Print_ISBN

978-1-4673-2184-6

Type

conf

DOI

10.1109/ICMMT.2012.6230389

Filename

6230389