SRAM-based FPGA´s: testing the interconnect/logic interface

This paper address the problem of testing the configurable modules that interface the global interconnect and the logic cells of SRAM-based FPGAs. The Configurable Interface Modules (CIMs) are assumed to be implemented with FPGA multiplexers but the results can be easily extended to any type of interface module. First, it is demonstrated that an address bit Configurable Interface Multiplexer requires N=2ⁿ test configurations considering a stuck-at as well as a functional fault model. Second, a logic cell with a set of k input Configurable Interface Modules with n address bits is analysed and it is proven that the set of CIMs can be tested in parallel making the number of required test configurations equal to N=2ⁿ. Third, it is shown that the complete circuit, i.e. a m×m array of sets of k Configurable Interface Multiplexers with n address bits can be tested with only N=2ⁿ test configurations using the XOR tree and shift register structures