DocumentCode
2496985
Title
Built-in self-test for multiple CLB faults of a LUT type FPGA
Author
Itazaki, Noriyoshi ; Matsuki, Fumiro ; Matsumoto, Yasuyuki ; Kinoshita, Kozo
Author_Institution
Dept. of Appl. Phys., Osaka Univ., Japan
fYear
1998
fDate
2-4 Dec 1998
Firstpage
272
Lastpage
277
Abstract
A new Built-in Self Test (BIST) method for multiple configurable logic block (CLB) faults of SRAM-Look-Up-Table (LUT) type FPGA is reported. In this method, self test is performed concurrently for every test block containing eight CLBs. Faulty FPGA which includes up to five faulty CLBs in one test block can be detected completely even if each faulted CLB includes unlimited number of faults
Keywords
built-in self test; fault location; field programmable gate arrays; integrated circuit testing; logic testing; table lookup; BIST method; LUT type FPGA; SRAM-look-up-table type; built-in self-test; configurable logic block faults; multiple CLB faults; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Electrical fault detection; Fault detection; Field programmable gate arrays; Logic devices; Logic testing; Performance evaluation; Table lookup; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium, 1998. ATS '98. Proceedings. Seventh Asian
ISSN
1081-7735
Print_ISBN
0-8186-8277-9
Type
conf
DOI
10.1109/ATS.1998.741624
Filename
741624
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