Title :
Fault tolerance of a tree-connected multiprocessor system and its arraylike layout
Author :
Nakano, Sumito ; Kamiura, Naotake ; Hata, Yutaka
Author_Institution :
Dept. of Comput. Eng., Himeji Inst. of Technol., Hyogo, Japan
Abstract :
In this paper, we discuss a reconfigurable tree-connected multiprocessor system and its arraylike layout. Each level in our tree consists of several blocks with PEs. The reconfiguration is executed for each block by shifting PEs to the right. It is valid if the number of faulty PEs in each block is less than or equal to that of spare ones in it. We introduce a 7×7 square module with a five-level tree to simplify the arraylike layout. The system with six or more levels is constructed easily by arranging several modules regularly. The comparison with other trees layoutable in planar arrays shows that our tree is superior to others in maximum interconnection length
Keywords :
fault tolerant computing; multiprocessor interconnection networks; reconfigurable architectures; arraylike layout; fault tolerance; five-level tree; maximum interconnection length; planar arrays; reconfigurable multiprocessor system; tree-connected multiprocessor system; Binary trees; Buildings; Circuit faults; Control systems; Fault tolerant systems; Integrated circuit interconnections; Multiplexing; Multiprocessing systems; Pediatrics; Planar arrays; Wafer scale integration;
Conference_Titel :
Test Symposium, 1998. ATS '98. Proceedings. Seventh Asian
Print_ISBN :
0-8186-8277-9
DOI :
10.1109/ATS.1998.741630
