Title :
Consequences of port restrictions on testing address decoder faults in two-port memories
Author :
Hamdioui, S. ; van de Goor, A.J.
Author_Institution :
Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
Abstract :
Testing two-port memories requires the use of single-port tests as well as special two-port tests; the test strategy determines which tests have to be used. Many two-port memories have ports which are read-only or write-only; this impacts the possible tests for single-port and two-port memories, as well as the test strategy. This paper discusses the consequences of the port restrictions (read-only or write-only ports) on the tests; in addition it covers the test strategy for address decoder faults in two-port memories
Keywords :
SRAM chips; fault location; integrated circuit testing; address decoder faults; memory testing; port restrictions; read-only ports; static RAM; test strategy; two-port memories; write-only ports; Computer architecture; Decoding; Electronic mail; Information technology; Interference; Performance evaluation; Random access memory; Read-write memory; System testing;
Conference_Titel :
Test Symposium, 1998. ATS '98. Proceedings. Seventh Asian
Print_ISBN :
0-8186-8277-9
DOI :
10.1109/ATS.1998.741636
